Altera CPRI IP Core - Manual (Page 61)

Chapter 4: Functional Description 4–29
MAP Interface
December 2013 Altera Corporation CPRI MegaCore Function
User Guide
On the CPRI side of the mapN Tx buffer, the MAP transmitter interface reads data
from the mapN Tx buffer and sends it to the CPRI transmitter interface. The offset
programmed in the
CPRI_MAP_OFFSET_TX register tells the MAP transmitter interface
when to reset the read pointer of the mapN Tx buffer and start transferring data from
the buffer to the CPRI transmitter interface. The K counter is reset to zero at the same
time, so that it advances from zero with the transfer of the data to the CPRI
transmitter interface, tracking the packing of the AxC container block contents into
the CPRI frame.
Because the mapN Tx buffer should not be read before it is written, the offset specified
in the
CPRI_START_OFFSET_TX register must precede the offset specified in the
CPRI_MAP_OFFSET_TX register. The CPRI IP core informs you of buffer overflow and
underflow (in the CPRI_IQ_TX_BUF_STATUS register described in Table 7–49 on
page 7–22 and as reported in the mapN_tx_status_data output vector described in
Table 6–2 on page 6–4 ), but it does not prevent them from occurring. Altera
recommends that you implement a separate tracking protocol to ensure you do not
overflow or underflow the mapN Tx buffer.
In synchronous buffer mode, because programmed offsets control the mapN Tx buffer
pointers, the delay through each mapN Tx buffer can be quantified.
MAP Transmitter in the Internally-clocked Mode
In the internally-clocked mode, each data channel, or AxC interface, has an output
ready signal,
mapN_tx_ready . Each AxC interface asserts its ready signal when it is
ready to receive data on this data channel for transmission to the CPRI protocol
interface—when the buffer level is at or below the threshold indicated in the
CPRI_MAP_TX_READY_THR register.
After the CPRI IP core asserts the mapN_tx_ready signal, the application is expected to
respond by asserting the mapN_tx_valid signal and presenting data on mapN_tx_data .
In every cpri_clkout cycle in which mapN_tx_ready is asserted, the application can
present valid data on mapN_tx_data , as prescribed by the Avalon-ST specification with
READY_LATENCY value 1.
For details about the behavior of the individual signals in the internally-clocked
mode, refer to
“MAP Transmitter Signals” on page 6–3 .