Altera CPRI IP Core - Manual (Page 34)

4–2 Chapter 4: Functional Description
Architecture Overview
CPRI MegaCore Function December 2013 Altera Corporation
User Guide
Architecture Overview
Figure 4–1 shows the main blocks of the CPRI IP core.
The Altera CPRI IP core supports the following interfaces:
■ MAP Interface
■ Auxiliary Interface
■ Media Independent Interface to an External Ethernet Block
■ CPU Interface
■ CPRI link interface described in CPRI Protocol Interface Layer (Physical Layer)
Information about the signals on the individual interfaces is available in the following
sections and in
Chapter 6, Signals .
The following sections describe the individual interfaces and clocks.
Figure 4–1. CPRI IP Core Block Diagram
Notes to Figure 4–1 :
(1) You can configure your CPRI IP core with zero, one, or multiple IQ data channels.
(2) You can configure your CPRI IP core with an Ethernet MAC block or an MII block. The two options are mutually exclusive.
(3) You can configure your CPRI IP core with or without an HDLC block.
AxC
IF
1
(1)
AxC
IF
24
(1)
... CPU Interface Module
Registers
tx_dataout
IQ Data Channels
(Optional) CPU Interface MI Interface
Transmitter
Transceiver
Transmitter
rx_datain
CPRI Link CPRI Link
Receiver
Transceiver
Receiver
Physical Layer
AUX Interface
Ethernet
(2)
MII
(2)
VSS/
Inband/
Alarms
HDLC
(3)
Control and Management
Module
CPRI MAP
Interface Module
RX Delay Measurement
and TX Calibration
Block