Dynamic pipelining for, Dynamic pipelining for automatic – Altera CPRI IP Core User Manual
Page 197
Appendix E: Delay Measurement and Calibration
E–19
Single-Hop Delay Measurement
December 2013
Altera Corporation
CPRI MegaCore Function
User Guide
The
rx_round_trip_delay
field of the
CPRI_ROUND_DELAY
register records the delay
between the outgoing
cpri_tx_rfp
signal and the outgoing
cpri_rx_rfp
signal. The
cpri_tx_rfp
signal is bit [0] of the
aux_tx_status_data
output signal bus, asserted in
response to the assertion of the incoming signal
cpri_tx_sync_rfp
, which is bit [64] of
the
aux_tx_mask_data
input signal, or in response to the 10 ms radio frame start based
on the internal frame count in the CPRI transmitter interface. The
cpri_rx_rfp
signal
is bit [75] of the
aux_rx_status_data
output signal bus, asserted in response to the
start of the 10 ms radio frame on the CPRI receiver interface.
The CPRI IP core does not provide the values of
T12
and
T34
. Use the following
process to calculate the round-trip cable delay
T14
in
cpri_clkout
cycles:
T14 = rx_round_trip_delay
– <REC Rx path delay> – <REC Tx path delay>
where
■
rx_round_trip_delay
is the value in the
CPRI_ROUND_DELAY
register at offset
0x38 (
)
■
<REC Rx path delay> is the Rx path delay, described in
, for the values in the CPRI REC master
■
<REC Tx path delay> is the Tx path delay, described in
, for the values in the CPRI REC master
1
Because the CPRI REC master and the CPRI RE slave might be on different
devices, these formulas specify the source CPRI IP core (REC or RE) for the
delays in each calculation.
The round-trip cable delay in a single-hop system is
Round-trip cable delay
= T14
– Toffset
Tx Bitslip Delay in the Round-Trip Delay Calculation
The Tx bitslip delay that a CPRI RE slave adds to the delay through the transceiver
transmitter compensates for the word aligner bitslip delay in the transceiver receiver.
The total of these two bit values is added to a detailed round-trip delay calculation,
because the two delays are included in the respective transceiver delay. However, the
total of these two bit values does not reach the duration of a single
cpri_clkout
cycle,
nor does it reach the threshold of the CPRI specification R-20 and R-21 requirements.
The bitslip delay is noticeable only with an oscilloscope.
Refer to
“Tx Bitslip Delay” on page E–14
for the details of this feature.
Dynamic Pipelining for Automatic Round-Trip Delay Calibration
The CPRI IP core provides an additional, optional mechanism to help minimize the
variation in the round-trip delay through a CPRI REC or RE master. The CPRI IP core
is configured with a set of n (currently five) pipelined registers following the Rx
elastic buffer in the Rx path. This feature is turned off by default in the IP core
parameter editor. When this feature is turned off, the calibration pointer latency is
zero and you should deduct one
cpri_clkout
clock cycle from the
T_R1
value as
stated in
Table E–3
. If this feature is turned on and the
cal_en
bit in the
CPRI_AUTO_CAL
register has the value of 1, the autocalibration feature is active. The user programs the
cal_rtd
field of the
CPRI_AUTO_CAL
register with the expected number of
cpri_clkout