Altera CPRI IP Core - Manual (Page 193)

Appendix E: Delay Measurement and Calibration E–15
Single-Hop Delay Measurement
December 2013 Altera Corporation CPRI MegaCore Function
User Guide
The CPRI IP core reports the Rx bitslip through the word aligner in the
rx_bitslipboundaryselectout field of the CPRI_TX_BITSLIP register, and
compensates for this variable delay by adding a bitslip in the Tx path. The current
size of this bitslip in bits is available in the
tx_bitslipboundaryselect field of the
CPRI_TX_BITSLIP register. When you leave the tx_bitslip_en field at its default
value of 0, this feature is active.
The Tx bitslip feature ensures stability in the round-trip delay through a CPRI RE
core, but introduces a variable component in each of the Tx and Rx paths when
considered independently. In CPRI IP cores in master clocking mode, the
tx_bitslipboundaryselect field has the constant value of 0.
If you set the value of the tx_bitslip_en field to 1, you can override the current
tx_bitslipboundaryselect value to control the Tx bitslip delay manually. Altera
does not recommend implementing the manual override.
In CPRI IP core variations that target an Arria V, Cyclone V, or Stratix V device,
the Tx bitslip functionality is included in the Altera PHY IP core that is generated
with the CPRI IP core. These variations include the
CPRI_TX_BITSLIP register to
support manual override of the Tx bitslip delay.
1
Altera does not recommend implementing the manual override for the Tx
bitslip.
Tx Transceiver Latency
The Altera high-speed transceiver is implemented using the deterministic latency
protocol, which ensures that delays in byte alignment within the transceiver are
consistent.
In all CPRI IP core variations except those that target an Arria V GT device and
are configured with the CPRI line rate of 9.8 Gbps, the delay through the Tx
transceiver is a fixed delay.