Altera CPRI IP Core User Manual
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Chapter 1: About This MegaCore Function
CPRI IP Core Features
CPRI MegaCore Function
December 2013
Altera Corporation
User Guide
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Supports the following additional CPRI link features:
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Programmable CPRI communication line rate (to 614.4, 1228.8, 2457.6, 3072.0,
4915.2, 6144.0, or 9830.4 Mbps) using Altera on-chip high-speed transceivers.
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Programmable operation mode: CPRI link master or CPRI link slave.
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Auto-rate negotiation support.
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Scrambling and descrambling at 4915.2 Mbps, 6144.0 Mbps, and 9830.4 Mbps.
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Receiver (Rx) delay measurement.
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Transmitter (Tx) delay calibration.
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Programmable hardware processing of the reset request bit in the CPRI frame.
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Vendor-specific subchannel (VSS) communication on the CPRI link.
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Diagnostic parallel reverse loopback paths.
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Diagnostic stand-alone RE slave testing mode.
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Includes the following additional interfaces:
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Interface to external or on-chip processor, using the Altera Avalon
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Memory-Mapped (Avalon-MM) interconnect specification.
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Ethernet communication interfaces that support simultaneous Ethernet and
HDLC communication to and from the CPRI link.
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Optional configuration of Ethernet MAC.
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Optional Media-Independent Interface for Ethernet frame access.
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Optional configuration of HDLC block.
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Auxiliary interface provides full access to CPRI frame.
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Supports data transfer to and from custom mapping functions, including
user-defined GSM mapping.
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Supports data transfer from slave to master ports to implement daisy-chain
topologies.
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Supports custom IQ sample widths.
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Optional built-in IQ data interface with the following features:
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Implements mapping methods in Sections 4.2.7.2.5 and 4.2.7.2.7 of the CPRI
V4.2 Specification, and mapping Options 1 and 2 in Sections 4.2.7.2.3 and
4.2.7.2.4 of the CPRI V4.2 Specification.
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Implements WiMAX mapping methods described in Sections 4.2.7.2.2,
4.2.7.2.5, and 4.2.7.2.7 of the CPRI V4.2 Specification.
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Implements UMTS/LTE mapping methods described in Section 4.2.7.2 of
the CPRI V4.2 Specification.
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Implements WiMAX timing control methodology described in Section
4.2.8.2 of the CPRI V4.2 Specification.
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Supports as many as 24 antenna-carrier interfaces.
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Supports clocking antenna-carrier interfaces with external data channel
clocks or internal IP core clock.