Cpri ip core features, Cpri ip core features –3 – Altera CPRI IP Core User Manual

Page 9

Chapter 1: About This MegaCore Function

1–3

CPRI IP Core Features

December 2013

Altera Corporation

CPRI MegaCore Function

User Guide

Figure 1–2

shows the CPRI IP core interfaces. The IP core assembles the outbound

CPRI frame control words and data from all of these interfaces, and unloads and
routes control words and data from the inbound CPRI frame to the appropriate
interfaces, based on configuration and register settings.

CPRI IP Core Features

The CPRI IP core has the following features:

■

Complies with the

Common Public Radio Interface (CPRI) Specification V5.0

(2011-09-21) Interface Specification

for wireless base station submodule

interconnections, without the full range of IQ data sample widths, using auxiliary
interface for user-defined GSM mapping.

■

Supports radio equipment controller (REC) and radio equipment (RE) module
configurations, including RE master, RE slave, and REC master ports.

■

Supports Universal Mobile Telecommunication System (UMTS) Terrestrial Radio
Access (UTRA) – frequency division duplexing (UTRA-FDD) (UMTS/Wideband
Code Division Multiple Access (W-CDMA)), Evolved UTRA (E-UTRA) (3rd
Generation Partnership Project (3GPP) Long Term Evolution (LTE) specification),
3GPP Global System for Mobile Communications (GSM)/Enhanced Data Rates for
GSM Evolution (EDGE) Radio Access Network, and Worldwide interoperability
for Microwave Access (WiMAX) (IEEE 802.16 standard).

■

Provides full access to CPRI frame.

Figure 1–2. CPRI IP Core Interfaces

Notes to

Figure 1–2

(1) You can configure your CPRI IP core with zero, one, or multiple antenna-carrier interfaces. If you configure zero antenna-carrier interfaces, the

MAP interface is not configured in your CPRI IP core. In that case you can communicate IQ data through the AUX interface to your user-defined
routing layer.

(2) You can configure your CPRI IP core with or without an HDLC block.

(3) You can configure your CPRI IP core with an Ethernet MAC block or a media-independent (MI) interface (MII) block. The two options are mutually

exclusive.

tx_dataout

Transmitter

Transceiver

Transmitter

rx_datain

CPRI Link

Receiver

Transceiver

Receiver

Multiplexing

Time Division Multiplexing

Data

Full access

CPRI frame

Vendor

Specific

Inband

Protocol

HDLC

(2)

Ethernet

(3)

MAP

Interface

(1)

AUX

Interface

CPU

Interface