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Arria v gt 9.8 gbps – Altera CPRI IP Core User Manual

Page 195

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Appendix E: Delay Measurement and Calibration

E–17

Single-Hop Delay Measurement

December 2013

Altera Corporation

CPRI MegaCore Function

User Guide

Arria V GT 9.8 Gbps

Arria V GT 9.8 Gbps variations use a soft PCS, and are a special case. The following
sections describe the Tx delay through this variant.

Figure E–6

shows the Tx path delay components in a CPRI IP core variation that

targets an Arria V GT device and was originally configured with the CPRI line rate of
9.8 Gbps. This figure also illustrates the Tx path delay components in Arria V GT
variations whose CPRI line rate was auto-negotiated down from the configured CPRI
line rate of 9.8 Gbps to a lower line rate.

The Tx path delay from the AUX interface comprises the following delays:

1. Fixed delay from the Aux interface through the CPRI low-level transmitter to the

transceiver PCS. This delay is 7

cpri_clkout

clock cycles.

2. Delay through the transceiver. This delay has the following components.

a. Variable Tx bitslip delay in CPRI RE slaves.

b. Fixed delay through the soft PCS.

c. Variable delay through the Tx buffer between the soft PCS and the PMA.

d. Fixed delay through the PMA configured with the Altera Native PHY IP core.

Fixed Tx Core Delay Component

This delay is 7

cpri_clkout

clock cycles.

Delay through the Transceiver

The following sections describe the delays through the transceiver.

Variable Tx Bitslip Delay

This delay does not exist for CPRI IP cores in master clocking mode. Refer to

“Tx

Bitslip Delay” on page E–14

for information about

tx_bitslip

.

Transceiver Fixed Delay

This delay is the sum of the fixed delay through the soft PCS and the fixed delay
through the PMA. This delay is shown in the last column of

Table E–7 on

page E–16

.

Figure E–6. Tx Path Delay to CPRI Link in Arria V GT Variations Configured with a CPRI Line Rate of 9.8 Gbps

AxC IF 0

AxC IF n

...

AUX Interface

Data Channels

Transmitter Transceiver

Transmitter

tx_dataout

Physical Layer

CPRI MAP

Interface Module

AUX

Module

(1)

(1)

(2a)

(2b)

(2c)

(2d)