Altera CPRI IP Core - Manual (Page 28)

3–4 Chapter 3: Parameter Settings
Data Link Layer Parameters
CPRI MegaCore Function December 2013 Altera Corporation
User Guide
The value you specify for Receiver buffer depth is referred to as WIDTH_RX_BUF in
this user guide.
For more information about the Rx elastic buffer, refer to “Rx Elastic Buffer” on
page 4–54 .
Transceiver Reference Clock Frequency
If your CPRI variation targets an Arria V, Cyclone V, or Stratix V device, the
Transceiver reference clock frequency
parameter is available. Use this parameter to
modify the expected frequency of the CPRI transceiver input reference clock to the
frequency of an available clock for your design.
The frequency you specify is an input parameter to the Altera Deterministic Latency
PHY IP core that is included in your Arria V, Cyclone V, or Stratix V CPRI variation.
Values available at each CPRI line rate are the reference clock frequencies for which
the Deterministic Latency PHY IP core supports the target CPRI line rate. The default
value is 122.88 MHz.
In the case of an Arria V GT variation configured with CPRI line rate 9830.4 Mbps, the
frequency is an input parameter to the Altera Native PHY IP core.
f For more information about the Altera Deterministic Latency PHY IP core and the
Altera Native PHY IP core, refer to the
Altera Transceiver PHY IP Core User Guide .
Automatic Round-Trip Delay Calibration
Turn on the Automatic round-trip delay calibration parameter to specify that your
CPRI IP core includes the calibration logic. By default, the parameter is turned off.
f For more information on automatic round-trip calibration delay feature, refer to
“Dynamic Pipelining for Automatic Round-Trip Delay Calibration” on page E–19
Data Link Layer Parameters
This section lists the parameter that affects the configuration of the data link layer of
the CPRI IP core.
Include MAC Block
Turn on the Include MAC block parameter to specify that your CPRI IP core includes
an internal Ethernet MAC block. By default, this parameter is turned off. If this
parameter is turned off, the CPRI IP core implements the media-independent
interface (MII) to your own external Ethernet MAC, instead.
If this parameter is turned off in your CPRI IP core, your application cannot access the
Ethernet registers. Attempts to access these registers read zeroes and do not write
successfully, as for a reserved register address.
For information about the internal Ethernet MAC block, refer to “Accessing the
Ethernet Channel” on page 4–47 .
For information about the MII, refer to “Media Independent Interface to an External
Ethernet Block” on page 4–37 .