Altera CPRI IP Core User Manual
Page 40

4–8
Chapter 4: Functional Description
Clocking Structure
CPRI MegaCore Function
December 2013
Altera Corporation
User Guide
shows the clocking scheme for a CPRI IP core that targets an Arria V GT
device and is configured with a CPRI line rate of 9830.4 Mbps, configured or
programmed as an RE slave.
Figure 4–4. CPRI IP Core Slave Clocking in Arria V GT 9.8 Gbps Variations
Notes to
(1) In slave clocking mode, the
usr_clk
and
usr_pma_clk
input clocks must be driven by a common source from the cleanup PLL. For additional
constraints these clocks require, refer to
CPRI MegaCore Function
clk_ex_delay
pll_clkout
cpri_clkout
usr_clk
(245.76 MHz)
usr_pma_clk
(122.88 MHz)
gxb_refclk
gxb_pll_inclk
tx_clkout
TX
Buffer
RX
Buffer
122.88 MHz
122.88 MHz
Soft
PCS
Soft
PCS
tx_clkout
rx_clkout
Transceiver
Native PHY
IP Core
CPRI TX
MII Interface
CPU
Interface
CPRI RX
FIFO
Buffer
cpu_clk
mapN_tx_clk
FIFO
Buffer
mapN_rx_clk
CPRI Rx
MAP
Interface
CPRI Tx
MAP
Interface
cpri_mii_txclk
cpri_mii_rxclk
Clean-Up PLL
- MAX 10 JTAG (15 pages)
- MAX 10 Power (21 pages)
- Unique Chip ID (12 pages)
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- Device-Specific Power Delivery Network (28 pages)
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- Hybrid Memory Cube Controller (69 pages)
- ALTDQ_DQS IP (117 pages)
- MAX 10 Embedded Memory (71 pages)
- MAX 10 Embedded Multipliers (37 pages)
- MAX 10 Clocking and PLL (86 pages)
- MAX 10 FPGA (26 pages)
- MAX 10 FPGA (56 pages)
- USB-Blaster II (22 pages)
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- Cyclone V Avalon-MM (166 pages)
- Cyclone III FPGA Starter Kit (36 pages)
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- Stratix V Avalon-ST (293 pages)
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- LVDS SERDES Transmitter / Receiver (72 pages)
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- IP Compiler for PCI Express (372 pages)
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- RAM-Based Shift Register (26 pages)
- RAM Initializer (36 pages)
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- DCFIFO (28 pages)