Compiling and programming the device, Instantiating multiple cpri ip cores – Altera CPRI IP Core User Manual
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Chapter 2: Getting Started
Compiling and Programming the Device
CPRI MegaCore Function
December 2013
Altera Corporation
User Guide
In addition, before you compile your system to generate an SRAM Object File (.sof)
with which to configure your device, Altera recommends that you create assignments
for the high-speed transceiver VCCH settings.
To create assignments for the high-speed transceiver VCCH settings, perform the
following steps:
1. In the Quartus II window, on the Assignments menu, click Assignment Editor.
2. In the <
CPRI IP core instance
gxb_txdataout
signal.
3. Double-click in the Assignment Name column and click I/O Standard.
4. Double-click in the Value column and click your standard (for example, 1.5-V
PCML)
.
5. In the new <
2
to
4
for your CPRI IP core instance
gxb_rxdatain
signal.
f
For information about timing analyzers, refer to the Quartus II Help and the “Timing
Analysis” section in
Quartus II Handbook.
Compiling and Programming the Device
You can use the Start Compilation command on the Processing menu in the
Quartus II software to compile your design. After successfully compiling your design,
program the targeted Altera device with the Programmer and verify the design in
hardware.
1
Before compiling your CPRI IP core or other incomplete CPRI design in the Quartus II
software, you must assign unconnected CPRI IP core signals to virtual pins.
f
For information about compiling your design in the Quartus II software, refer to the
chapter in
volume 1 of the Quartus II Handbook. For information about programming an Altera
device, refer to the “Device Programming”
the Quartus II
Handbook.
Instantiating Multiple CPRI IP Cores
If you want to instantiate multiple CPRI IP cores in an Arria II, Cyclone IV GX, or
Stratix IV GX device, to ensure your design optimizes its use of device pins, you must
observe the following additional requirements: