Altera CPRI IP Core - Manual (Page 199)

Appendix E: Delay Measurement and Calibration E–21
Single-Hop Delay Measurement
December 2013 Altera Corporation CPRI MegaCore Function
User Guide
Round-Trip and Cable Delay Calculation Examples
This section shows you how to calculate the round-trip cable delay in your system.
The
CPRI_ROUND_DELAY register value and the Rx and Tx elastic buffer delays in the
examples are derived from hardware.
Round-Trip and Cable Delay Calculation Example 1: Two Stratix IV GX Devices
The example walks through the calculation for the case of two link partner CPRI IP
cores configured on Stratix IV GX devices, in a single-hop configuration, running at
CPRI data rate 6.144 Gbps. In both devices, the
rx_byte_delay field of the
CPRI_RX_DELAY register has the value of 0 and the cal_en field of the CPRI_AUTO_CAL
register has the value of 0. Both IP cores are configured with autorate negotiation
disabled.
To calculate the round-trip cable delay in this system, perform the following steps:
1. Read the value in the rx_round_trip_delay field of the CPRI_ROUND_DELAY register
(at register offset 0x38) of the REC master. For the example, the value is 0x6D,
which is decimal 109.
2. For each of the REC master and the RE slave, read the value in the
rx_ex_buf_delay field of the CPRI_EX_DELAY_STATUS register (at register offset
0x40) and the value in the ex_delay field of the CPRI_EX_DELAY_CONFIG register.
Read the rx_ex_buf_delay field only after the ex_buf_delay_valid bit in the
register is high.
3. For each of the REC master and the RE slave, divide the value in the
rx_ex_buf_delay register field by the value in the ex_delay register field. The
result is the current Rx elastic buffer delay in cpri_clkout cycles. In this example,
the Rx elastic buffer delay in the REC master is 10.5 cpri_clkout cycles, and the Rx
elastic buffer delay in the RE slave is 31 cpri_clkout cycles.
4. Calculate the Rx path delay through the RE slave, by following the steps in
“Calculation Example: Rx Path Delay to AUX Output” on page E–9 .
In this example, the value in the rx_bitslipboundaryselectout field of the
CPRI_TX_BITSLIP register is 0x8. Therefore, according to Table E–1 on page E–5 ,
and the table notes that describe how to calculate Tx_txv_RX in the case that
rx_bitslipboundaryselectout has a non-zero value, the correct value of
T_txv_RX is 7 cpri_clkout cycles.
According to Table E–3 on page E–8 , the correct value of T_R1 is 5 cpri_clkout
cycles. The Rx buffer delay is 10.5 cpri_clkout cycles, the rx_byte_delay register
field value is 0, and the cal_pointer register field value is 3, yielding a total delay
of 25.5 cpri_clkout cycles.
25.5 = <fixed T_txv_RX delay through transceiver> + <Rx buffer delay> + 0 + 3 + <fixed
core delay>
= 7 + 10.5 + 3 + 5
5. Calculate the Rx path delay through the REC master, by following the steps in
“Calculation Example: Rx Path Delay to AUX Output” on page E–9 .
In this example, the value in the rx_bitslipboundaryselectout field of the
CPRI_TX_BITSLIP register is 0x7. Therefore, according to Table E–1 on page E–5 ,
and the table notes that describe how to calculate Tx_txv_RX in the case that