Nortel Networks Circuit Card 311 - Manual (Page 911)

Functional description 911
• external timing interface
The main functional blocks of the NTAK20 architecture include:
• phase difference detector circuit
• digital phase-lock loop
• clock detection circuit
• digital-to-analog converter
• CPU MUX bus interface
• signal conditioning drivers and buffers
• sanity timer
• microprocessor
• CPU interface
• external timing interface
A description of each block follows.
The main functional blocks of the NTAK20 architecture include:
• phase difference detector circuit
• digital Phase Locked Loop (PLL)
• clock detection circuit
• digital-to-analog converter
• CPU MUX bus interface
• signal conditioning drivers and buffers
• sanity timer
• microprocessor
• CPU interface
• external timing interface
Phase difference detector circuit
This circuit, under firmware control, enables a phase difference
measurement to be taken between the reference entering the PLL and
the system clock.
The phase difference is used for making frequency measurements and
evaluating input jitter and PLL performance.
This circuit, under firmware control, allows a phase difference measurement
to be taken between the reference entering the PLL and the system clock.
Nortel Communication Server 1000
Circuit Card Reference
NN43001-311 01.04 Standard
Release 5.0 23 May 2008
Copyright © 2003-2008, Nortel Networks
.