FUJITSU F2MC-8L F202RA - Manual (Page 324)

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CHAPTER 13 UART
Figure 13.6-5 Operations in Operating Mode 0, 1, or 3 when the Overrun Error Occurs
Figure 13.6-6 Operations in Operating Mode 0, 1, or 3 when the Framing Error Occurs
Note:
After initialization is cancelled due to a reset, time for 11 shift-clock cycles is required to initialize the
internal controller. Therefore, be sure to enable the UART prescaler operation (PREN = 1) using the
oscillation frequency register after a reset.
ORFE
STOP START 0 1 2 3 4 5 6 7
RDRF=1
Data
(reception buffer full)
Reception interrupt
ORFE
STOP START 0 1 2 3 4 5 6 7
RDRF=0
Data
Reception interrupt