FUJITSU F2MC-8L F202RA - Manual (Page 137)

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CHAPTER 5 TIME-BASE TIMER
5.4 Interrupt of Time-base Timer
The time-base timer counter generates an interrupt when the specified bit of the counter
overflows (interval timer function).
■ Interrupts when the Interval Timer Function is Enabled
The counter counts up with the internal count clock. When the specified interval timer bit overflows, the
overflow interrupt request flag bit (TBTC: TBOF) is set to "1". Then if the interrupt request enable bit is
enabled (TBTC: TBIE = 1), an interrupt request (IRQ7) is sent to the CPU. When this occurs, use the
interrupt handling routine and set the TBOF bit to "0" to clear the interrupt request. The TBOF bit is set to
"1" when the specified bit overflows regardless of the value of the TBIE bit.
Note:
When the interrupt request is allowed to be output (TBIE = 1) after a reset is released, clear the TBOF bit
(TBOF = 0) at the same time.
Note:
• An interrupt request is generated immediately after the TBIE bit is set from 0 (disable) to 1 (enable) if
the TBOF bit is "1".
• When the counter is cleared (TBTC: TBR = 0) and the specified bit overflows at the same time, the
TBOF bit is not set.
■ Oscillation Stabilization Time and Time-base Timer Interrupts
If a time interval is set the time shorter than the oscillation stabilization time, the interval interrupt request
(TBTC: TBOF = 1) is generated from the time-base timer upon the start of normal mode. In this case,
interrupts from the time-base timer must be disabled (TBTC: TBIE = 0) when switching to stop mode in
which an oscillation is stopped.
■ Register and Vector Table Related to Interrupts from Time-base Timer
See Section "3.4.2 Steps in the Interrupt Operation " for details on interrupt operations.
Table 5.4-1 Register and Vector Table Related to Time-base Timer Interrupts
Interrupt name
Interrupt level setting register Address of vector table
Register Bits to be set High-order Low-order
IRQ7 ILR2 (007C
H
) L71 (bit7) L70 (bit6) FFEC
H
FFED
H