FUJITSU F2MC-8L F202RA - Manual (Page 104)

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CHAPTER 4 I/O PORTS
4.3.2 Operations of Port 3 Functions
This section describes the operation of port 3.
■ Operation of Port 3
●
Operation in output port mode
When "1" is written for a bit of the DDR3 register, the bit corresponding to a pin of port 3, the pin functions
as an output port.
In output port mode, output transistor operation is enabled and output latch data is output to the pin.
Once data has been written into the PDR3 register, the written data is held in the output latch and output to
the pin as it is.
The value state of the pin can be read by reading the PDR3 register.
●
Operation in input port mode
When "0" is written for a bit of the DDR3 register, the bit corresponding to a pin of port 3, the pin functions
as an input port.
In input port mode, the output transistor is OFF and the pin state is Hi-Z.
Once data has been written into the PDR3 register, the written data is held in the output latch but is not
output to the pin.
The value state of the pin can be read by reading the PDR3 register.
● Operation in external interrupt input mode
Set a bit of the DDR3 register to "0", the bit corresponding to a pin of port 3 that is to serve as an external
interrupt input pin, to set the pin to function as an input port.
The value state of the pin can be read by reading the PDR3 register regardless of whether or not the
external interrupt inputs or interrupt request outputs are enabled.
● Operation in mode enabling the output from a peripheral
When the output enable bit for a peripheral is set to enable, the corresponding pin is set to serve the output
from the peripheral.
Because the value state of the pin can be read from the PDR3 register even when the output from the
peripheral is enabled, the value output from the peripheral can be read.
●
Operation in mode enabling the input to a peripheral
Set a bit of the DDR3 register to "0", the bit corresponding to the pin of port 3 assigned for the input to the
desired peripheral, for the pin to function as an input port.
The value state of the pin is always input to the peripheral (except during stop mode).
The value state of the pin can be read by reading the PDR3 register regardless of whether or not the
peripheral is using the input pin.