Avago Technologies LSI53C895A - Manual (Page 99)

SCSI Bus Interface Signals 3-11
3.4 SCSI Bus Interface Signals
The SCSI Bus Interface signals section contains tables describing the
signals for the following signal groups:
SCSI Bus Interface Signals , SCSI
Signals , SCSI Control Signals .
3.4.1 SCSI Bus Interface Signal
Table 3.9 describes the SCSI Bus Interface signal.
Table 3.9 SCSI Bus Interface Signal
Name PQFP BGA Pos Type Strength Description
SCLK 80 J20 I N/A SCSI Clock is used to derive all
SCSI-related timings. The speed of this
clock is determined by the application’s
requirements. In some applications,
SCLK may be sourced internally from
the PCI bus clock (CLK). If SCLK is
internally sourced, then the SCLK pin
should be tied LOW. For Ultra2 SCSI
operations, the clock supplied to SCLK
must be 40 MHz. The clock frequency
will be quadrupled to create the
160 MHz clock required by the SCSI
core.