Avago Technologies LSI53C895A - Manual (Page 184)

4-76 Registers
Control Two (SCNTL2) register for more information on
expected versus unexpected disconnects. Any disconnect
in low level mode causes this condition.
RST SCSI Reset Condition 1
Indicates assertion of the SRST/ signal by the
LSI53C895A or any other SCSI device. This condition is
edge-triggered, so multiple interrupts cannot occur
because of a single SRST/ pulse.
PAR SCSI Parity Error 0
Indicates detection by the LSI53C895A of a parity error
while receiving or sending SCSI data. See the Disable
Halt on Parity Error or SATN/ Condition bits in the
SCSI
Control One (SCNTL1) register for more information on
when this condition is actually raised.
Register: 0x41
SCSI Interrupt Enable One (SIEN1)
Read/Write
This register contains the interrupt mask bits corresponding to the
interrupting conditions described in the
SCSI Interrupt Status One
(SIST1) register. An interrupt is masked by clearing the appropriate mask
bit. For more information on interrupts, refer to Chapter 2, “Functional
Description.”
R Reserved [7:5]
SBMC SCSI Bus Mode Change 4
Setting this bit allows the LSI53C895A to generate an
interrupt when the DIFFSENS pin detects a change in
voltage level that indicates the SCSI bus has changed
between SE, LVD, or HVD modes. For example, when
this bit is cleared and the SCSI bus changes modes, IRQ/
does not assert and the SIP bit in the
Interrupt Status
Zero (ISTAT0) register is not set. However, bit 4 in the
SCSI Interrupt Status One (SIST1) register is set. Setting
this bit allows the interrupt to occur.
7 5 4 3 2 1 0
R SBMC R STO GEN HTH
x x x 0 x 0 0 0