Avago Technologies LSI53C895A User Manual
Page 203
SCSI Registers
4-95
timers by greatly reducing all three time-out periods.
Setting this bit starts all three timers and if the respective
bits in the
SCSI Interrupt Enable One (SIEN1)
register
are asserted, the LSI53C895A generates interrupts at
time-out. This bit is intended for internal manufacturing
diagnosis and should not be used.
CSF
Clear SCSI FIFO
1
Setting this bit causes the “full flags” for the SCSI FIFO
to be cleared. This empties the FIFO. This bit is
self-clearing. In addition to the SCSI FIFO pointers, the
,
, and (SODR, a hidden buffer register which is not
accessible) full bits in the
and
are cleared.
STW
SCSI FIFO Test Write
0
Setting this bit places the SCSI core into a test mode in
which the FIFO is easily read or written. While this bit is
set, writes to the least significant byte of the
register cause the entire word
contained in the SODL to be loaded into the FIFO. These
functions are summarized in the table below.
Register
Name
Register
Operation
FIFO Bits
FIFO
Function
SODL
Write
[15:0]
Load
SODL0
Write
[7:0]
Load
SODL1
Write
[15:8]
None