Avago Technologies LSI53C895A - Manual (Page 308)

6-48 Electrical Specifications
Figure 6.29 Normal/Fast Memory (
≥ =
128 Kbytes) Multiple Byte Access Read Cycle
MAD
(Addr Driven by LSI53C895A;
MAS1/
(Driven by LSI53C895A)
MAS0/
(Driven by LSI53C895A)
MCE/
(Driven by LSI53C895A)
MOE/
(Driven by LSI53C895A)
MWE/
(Driven by LSI53C895A)
0 2 4 6 8 10 12 14 16 17
Data driven by Memory)
CLK
(Driven by System)
PAR
(Driven by LSI53C895A-
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C895A)
STOP/
(Driven by LSI53C895A)
DEVSEL/
(Driven by LSI53C895A)
AD
(Driven by LSI53C895A-
C_BE[3:0]/
(Driven by Master)
FRAME/
(Driven by Master)
Master-Addr; Data)
Master-Addr; Data)
Byte Enable
Addr In
CMD
Upper
Address
Middle
Address
Lower
Address
In