Avago Technologies LSI53C895A - Manual (Page 350)

IX-4 Index
B
base address register
one (BAR1) 2-3 , 4-9
two (BAR2) 4-10
zero - I/O (BAR0) 4-9
bidirectional 3-3
signals 6-5
BIOS 2-3
bits used for parity control and generation 2-27
block move 2-9
block move instructions 5-5
bridge support extensions (BSE) 4-18
burst
disable (BDIS) 4-60
length (BL[1:0]) 4-67
length bit 2 (BL2) 4-63
opcode fetch enable (BOF) 4-69
size selection 2-6
bus
command and byte enables 3-5
fault (BF) 4-41 , 4-70
byte
count 5-37
empty in DMA FIFO (FMT) 4-54
full in DMA FIFO (FFL) 4-54
offset counter (BO) 4-58
C
cache line size 2-7 , 2-9
(CLS) 4-7
enable (CLSE) 4-71
register 2-6
cache mode, see PCI cache mode 2-9
call instruction 5-27
Cap_I (CID) 4-15
capabilities pointer (CP) 4-13
carry test 5-30
chained block moves 2-51
SCRIPTS instruction 2-54
SODL register 2-54
SWIDE register 2-53
wide SCSI receive bit 2-53
wide SCSI send bit 2-52
chained mode (CHM) 4-27
change bus phases 2-19
chip
control 0 (CCNTL0) 4-98
control 1 (CCNTL1) 4-100
revision level (V) 4-57
test five (CTEST5) 4-62
test one (CTEST1) 4-54
test six (CTEST6) 4-63
test three (CTEST3) 4-57
test two (CTEST2) 4-55
test zero (CTEST0) 4-54
type (TYP) 4-83
CHMOV 2-51
class code (CC) 4-7
clear DMA FIFO 2-48 , 4-57
clear instruction 5-15 , 5-17
clear SCSI FIFO (CSF) 4-95
CLF 2-48
CLK 3-4
clock 3-4
address incrementor (ADCK) 4-62
byte counter (BBCK) 4-62
conversion factor (CCF[2:0]) 4-30
quadrupler 2-22
CLSE 2-6 , 2-7
CMP 2-45
compare
data 5-31
phase 5-31
configuration
read command 2-5
space 2-3
write command 2-6
configured
as I/O (CIO) 4-55
as memory (CM) 4-55
connected (CON) 4-25 , 4-50
CSF 2-48
CTEST4 2-27
cumulative SCSI byte count (CSBC) 4-112
cycle frame 3-6
D
D1_support (D1S) 4-16
D2_support (D2S) 4-16
DACs 2-21
data
(DATA) 4-18
acknowledge status (DACK) 4-56
compare mask 5-31
compare value 5-32
parity error reported (DPR) 4-6
paths 2-30
request status (DREQ) 4-56
structure address (DSA) 4-48
transfer direction (DDIR) 4-55
data read (DRD) 4-83
data write (DWR) 4-83
data_scale (DSCL) 4-17
data_select (DSLT) 4-17
data-in 2-54
data-out 2-54
DCNTL 2-6 , 2-45
decode of MAD pins 3-20
default download mode 2-57
destination
address 5-23
I/O memory enable (DIOM) 4-69
detected parity error (from slave) (DPE) 4-5
determining the data transfer rate 2-40
device
ID (DID) 4-3
select 3-7
specific initialization (DSI) 4-16
DEVSEL/ 3-7
timing (DT[1:0]) 4-6
DIEN 2-27 , 2-45 , 2-46
differential mode. See high voltage differential mode 2-35
diffsens mismatch (DM) 4-47
DIFFSENS SCSI signal 3-12 , 6-4
DIP 2-44 , 2-47 , 2-48 , 2-49
direct 5-19
disable
auto FIFO clear (DISFC) 4-99
dual address cycle (DDAC) 4-100