Avago Technologies LSI53C895A - Manual (Page 66)

2-40 Functional Description
Status Zero (SIST0) and SCSI Interrupt Enable Zero (SIEN0) registers,
respectively, indicating that the LSI53C895A has been selected (bit 5)
and reselected (bit 4).
2.2.15 Synchronous Operation
The LSI53C895A can transfer synchronous SCSI data in both the
initiator and target modes. The
SCSI Transfer (SXFER) register controls
both the synchronous offset and the transfer period. It may be loaded by
the CPU before SCRIPTS execution begins, from within SCRIPTS using
a Table Indirect I/O instruction, or with a Read-Modify-Write instruction.
The LSI53C895A can receive data from the SCSI bus at a synchronous
transfer period as short as 25 ns, regardless of the transfer period used
to send data. The LSI53C895A can receive data at one-fourth of the
divided SCLK frequency. Depending on the SCLK frequency, the
negotiated transfer period, and the synchronous clock divider, the
LSI53C895A can send synchronous data at intervals as short as 25 ns
for Ultra2 SCSI, 50 ns for Ultra SCSI, 100 ns for fast SCSI and 200 ns
for SCSI-1.
2.2.15.1 Determining the Data Transfer Rate
Synchronous data transfer rates are controlled by bits in two different
registers of the LSI53C895A. Following is a brief description of the bits.
Figure 2.7 illustrates the clock division factors used in each register, and
the role of the register bits in determining the transfer rate.