Avago Technologies LSI53C895A User Manual
Page 155
SCSI Registers
4-47
OLF1
SODL Most Significant Byte Full
5
This bit is set when the most significant byte in the
contains data. The SODL
register is the interface between the DMA logic and the
SCSI bus. In synchronous mode, data is transferred from
the host bus to the SODL register, and then to the SCSI
Output Data register (SODR, a hidden buffer register
which is not accessible) before being sent to the SCSI
bus. In asynchronous mode, data is transferred from the
host bus to the SODL register, and then to the SCSI bus.
The SODR buffer register is not used for asynchronous
transfers. It is possible to use this bit to determine how
many bytes reside in the chip when an error occurs.
FF4
FIFO Flags, Bit 4
4
This is the most significant bit in the SCSI FIFO Flags
field, when concatenated with bits [7:4] (FF[3:0]) in
. For a complete description of this
field, see the definition for
bits [7:4].
SPL1
Latched SCSI Parity for SD[15:8]
3
This active HIGH bit reflects the SCSI odd parity signal
corresponding to the data latched into the most
significant byte in the
register.
DM
Diffsens Mismatch
2
This bit is set when the DIFFSENS pin detects a SE or
LVD SCSI operating voltage level while the LSI53C895A
is operating in HVD mode (by setting the DIF bit in the
register). If this bit is cleared,
the DIFFSENS value matches the DIF bit setting.
LDSC
Last Disconnect
1
This bit is used in conjunction with the Connected (CON)
bit in
. It allows the user to
detect the case in which a target device disconnects, and
then some SCSI device selects or reselects the
LSI53C895A. If the Connected bit is asserted and the
LDSC bit is asserted, a disconnect is indicated. This bit
is set when the Connected bit in SCNTL1 is off. This bit
is cleared when a Block Move instruction is executed
while the Connected bit in SCNTL1 is on.