Avago Technologies LSI53C895A - Manual (Page 321)

SCSI Timing Diagrams 6-61
Table 6.47 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or 20.0 Mbytes
(16-Bit Transfers) 50 MHz Clock
1, 2
1. Transfer period bits (bits [7:5] in the SCSI Transfer (SXFER) register) are set to zero and the Extra
Clock Cycle of Data Setup bit (bit 7 in SCSI Control One (SCNTL1) ) is set.
2. For fast SCSI, set the TolerANT Enable bit (bit 7 in SCSI Test Three (STEST3) ).
Symbol Parameter Min Max Unit
t
1
Send SREQ/ or SACK/ assertion pulse width 30 – ns
t
2
Send SREQ/ or SACK/ deassertion pulse width 30 – ns
t
1
Receive SREQ/ or SACK/ assertion pulse width 22 – ns
t
2
Receive SREQ/ or SACK/ deassertion pulse width 22 – ns
t
3
Send data setup to SREQ/ or SACK/ asserted 24 – ns
t
4
Send data hold from SREQ/ or SACK/ asserted 40
3
3. Analysis of system configuration is recommended due to reduced driver skew margin in differential
systems.
– ns
t
5
Receive data setup to SREQ/ or SACK/ asserted 14 – ns
t
6
Receive data hold from SREQ/ or SACK/ asserted 24 – ns
Table 6.48 Ultra SCSI SE Transfers 20.0 Mbytes (8-Bit Transfers) or
40.0 Mbytes (16-Bit Transfers) Quadrupled 40 MHz Clock
1, 2
1. Transfer period bits (bits [7:5] in the SCSI Transfer (SXFER) register) are set to zero and the Extra
Clock Cycle of Data Setup bit (bit 7 in SCSI Control One (SCNTL1) ) is set.
2. During Ultra2 SCSI transfers, the value of the Extend REQ/ACK Filtering bit ( SCSI Test Two
(STEST2) , bit 1) has no effect.
Symbol Parameter Min Max Unit
t
1
Send SREQ/ or SACK/ assertion pulse width 15 – ns
t
2
Send SREQ/ or SACK/ deassertion pulse width 15 – ns
t
1
Receive SREQ/ or SACK/ assertion pulse width 11 – ns
t
2
Receive SREQ/ or SACK/ deassertion pulse width 11 – ns
t
3
Send data setup to SREQ/ or SACK/ asserted 12 – ns
t
4
Send data hold from SREQ/ or SACK/ asserted 17 – ns
t
5
Receive data setup to SREQ/ or SACK/ asserted 6 – ns
t
6
Receive data hold from SREQ/ or SACK/ asserted 11 – ns