Avago Technologies LSI53C895A - Manual (Page 212)

4-104 Registers
4.3 64-Bit SCRIPTS Selectors
The following registers are used to hold the upper 32-bit addresses for
various SCRIPTS operations. When a particular type of SCRIPTS
operation is performed, one of the six selector registers below will be
used to generate a 64-bit address.
If the selector for a particular device operation is zero, then a standard
32-bit address cycle will be generated. If the selector value is nonzero,
then a DAC will be issued and the 64-bit address will be presented in
two address phases.
All selectors default to 0 (zero) with the exception of the 16 SCRATCH
registers, these power-up in an indeterminate state and should be
initialized before they are used.
All selectors can be read/written using the Load and Store SCRIPTS
instruction, Memory-to-Memory Move, Read/Write SCRIPTS instruction,
or CPU with SCRIPTS not running.
Note: Crossing of selector boundaries in one memory operation
is not supported.
Registers: 0xA0–0xA3
Memory Move Read Selector (MMRS)
Read/Write
MMRS Memory Move Read Selector [31:0]
Supplies the upper Dword of a 64-bit address during data
read operations for Memory-to-Memory Moves and
absolute address LOAD operations.
A special mode of this register can be enabled by setting
the PCI Configuration Enable bit in the
Chip Test Two
(CTEST2) register. Because the LSI53C895A supports
only a 32-bit memory mapped PCI base address, the
MMRS register is always read as 0x00000000 when in
the special mode.
31 0
MMRS
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0