Avago Technologies LSI53C895A - Manual (Page 154)

4-46 Registers
SDP0L Latched SCSI Parity 3
This bit reflects the SCSI parity signal (SDP0/),
corresponding to the data latched in the
SCSI Input Data
Latch (SIDL) . It changes when a new byte is latched into
the least significant byte of the SIDL register. This bit is
active HIGH, in other words, it is set when the parity
signal is active.
MSG SCSI MSG/ Signal 2
C_D SCSI C_D/ Signal 1
I_O SCSI I_O/ Signal 0
These three SCSI phase status bits (MSG, C_D, and
I_O) are latched on the asserting edge of SREQ/ when
operating in either the initiator or target mode. These bits
are set when the corresponding signal is active. They are
useful when operating in the low level mode.
Register: 0x0F
SCSI Status Two (SSTAT2)
Read Only
ILF1 SIDL Most Significant Byte Full 7
This bit is set when the most significant byte in the SCSI
Input Data Latch (SIDL) contains data. Data is transferred
from the SCSI bus to the SCSI Input Data Latch register
before being sent to the DMA FIFO and then to the host
bus. The SIDL register contains SCSI data received
asynchronously. Synchronous data received does not
flow through this register.
ORF1 SODR Most Significant Byte Full 6
This bit is set when the most significant byte in the SCSI
Output Data register (SODR, a hidden buffer register
which is not accessible) contains data. The SODR
register is used by the SCSI logic as a second storage
register when sending data synchronously. It is not
accessible to the user. This bit is used to determine how
many bytes reside in the chip when an error occurs.
7 6 5 4 3 2 1 0
ILF1 ORF1 OLF1 FF4 SPL1 DM LDSC SDP1
0 0 0 0 x x 1 x