Avago Technologies LSI53C895A - Manual (Page 314)

6-54 Electrical Specifications
Figure 6.33
≤
64 Kbytes ROM Read Cycle
Table 6.38
≤ =
64 Kbytes ROM Read Cycle
Symbol Parameter Min Max Unit
t
11
Address setup to MAS/ HIGH 25 – ns
t
12
Address hold from MAS/ HIGH 15 – ns
t
13
MAS/ pulse width 25 – ns
t
14
MCE/ LOW to data clocked in 150 – ns
t
15
Address valid to data clocked in 205 – ns
t
16
MOE/ LOW to data clocked in 100 – ns
t
17
Data hold from address, MOE/, MCE/ change 0 – ns
t
18
Address out from MOE/, MCE/ HIGH 50 – ns
t
19
Data setup to CLK HIGH 5 – ns
CLK
MAD
(Address driven by LSI53C895A;
Data driven by Memory)
MAS1/
(Driven by LSI53C895A)
MAS0/
(Driven by LSI53C895A)
MCE/
(Driven by LSI53C895A)
MOE/
(Driven by LSI53C895A)
MWE/
(Driven by LSI53C895A)
Higher
Address
Lower
Address
Valid
Read
Data
t
17
t
12
t
15
t
14
t
18
t
16
t
19 t
11
t
13