Avago Technologies LSI53C895A - Manual (Page 274)

6-14 Electrical Specifications
Table 6.17 and Figure 6.10 provide Interrupt Output timing data.
Figure 6.10 Interrupt Output
6.4 PCI and External Memory Interface Timing Diagrams
Figures 6.11 through 6.34 represent signal activity when the
LSI53C895A accesses the PCI bus. This section includes timing
diagrams for access to three groups of memory configurations. The first
group applies to
Target Timing . The second group applies to Initiator
Timing . The third group applies to External Memory Timing .
Note: Multiple byte accesses to the external memory bus
increase the read or write cycle by 11 clocks for each
additional byte.
Timing diagrams included in this section are:
•
Target Timing
– PCI Configuration Register Read
– PCI Configuration Register Write
– 32-Bit Operating Register/SCRIPTS RAM Read
– 64-Bit Address Operating Register/SCRIPTS RAM Read
Table 6.17 Interrupt Output
Symbol Parameter Min Max Unit
t
1
CLK HIGH to IRQ/ LOW 2 11 ns
t
2
CLK HIGH to IRQ/ HIGH 2 11 ns
t
3
IRQ/ deassertion time 3 – CLK
CLK
IRQ/
t
3
t
1
t
2