Avago Technologies LSI53C895A - Manual (Page 352)

IX-6 Index
GPIO5 3-10
GPIO6 3-10
GPIO7 3-10
GPIO8 3-10
grant 3-8
H
halt SCSI clock (HSC) 4-94
halting 2-48
handshake-to-handshake timer
bus activity enable (HTHBA) 4-87
expired (HTH) 4-77 , 4-81
period (HTH[3:0]) 4-85
scale factor (HTHSF) 4-87
hardware control of SCSI activity LED 2-21
hardware interrupts 2-43
header type (HT) 4-8
high impedance mode (SZM) 4-92
high impedance mode (ZMODE) 4-100
high voltage differential interface 2-36
high voltage differential mode
autoswitching with LVD and single-ended mode 2-35
description 2-35
HVD or SE/LVD (DIF) 4-92
HVD signals 2-35
I
I/O 3-3
instructions 5-13
read command 2-5
space 2-2 , 2-3
write command 2-5
IDSEL 2-3 , 3-7
signal 2-5
illegal instruction detected (IID) 4-41 , 4-70
immediate
arbitration (IARB) 4-25
data 5-23
indirect addressing 5-6
initialization device select 3-7
initiator
mode 5-16
phase mismatch 4-78
ready 3-7
input 3-3
capacitance 6-4
instruction
address (IA) 4-111
prefetch unit flushing 2-23
type 5-36
block move 5-6
I/O instruction 5-13
memory move 5-33
read/write instruction 5-22
transfer control instruction 5-26
instructions
block move 5-5
interface control signals 3-6
internal
SCRIPTS
RAM 2-20
internal RAM
see also SCRIPTS
RAM 2-20
interrupt
acknowledge command 2-4
handling 2-43
instruction 5-28
line (IL) 4-13
on-the-fly 5-30
on-the-fly (INTF) 4-50
output 6-14
pin (IP) 4-14
request 2-43 , 3-9
signals 3-9
status (ISTAT0) 4-48
status one (ISTAT1) 4-52
interrupt select (ISEL[1:0]) 4-91
interrupt-on-the-fly instruction 5-28
interrupts 2-45
fatal vs. nonfatal interrupts 2-45
halting 2-48
IRQ disable bit 2-45
masking 2-46
sample interrupt service routine 2-49
stacked interrupts 2-47
IRDY/ 3-7
IRQ disable (IRQD) 4-73
IRQ mode (IRQM) 4-73
IRQ/ 2-43 , 3-9
IRQ/ pin 2-46 , 2-49
issuing cache commands 2-10
ISTAT 2-43 , 2-49
J
JTAG boundary scan testing 2-25
jump
address 5-32
call a relative address 5-29
call an absolute address 5-29
control (PMJCTL) 4-98
if true/false 5-30
instruction 5-27
L
last disconnect (LDSC) 4-47
latched SCSI parity
for SD[15:8] (SPL1) 4-47
latched SCSI parity (SDP0L) 4-46
latency 2-9
timer (LT) 4-8
LED_CNTL (LEDC) 4-84
load and store 5-37
load and store instructions 2-24
prefetch unit and store instructions 2-24
loading mechanism 2-58
loopback enable 2-26
lost arbitration (LOA) 4-44
low voltage differential. See LVDlink 2-34
LSI53C700 compatibility (COM) 4-73
LSI53C895A
new features 1-3
LVD
driver SCSI signals 6-3
receiver SCSI signals 6-3
SCSI 1-4
LVDlink 1-1 , 1-4
benefits 1-4
operation 2-34