Avago Technologies LSI53C895A - Manual (Page 311)

PCI and External Memory Interface Timing Diagrams 6-51
Figure 6.30 Normal/Fast Memory (
≥ =
128 Kbytes) Multiple Byte Access Write Cycle
(Cont.)
CLK
(Driven by System)
PAR
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C895A)
STOP/
(Driven by LSI53C895A)
DEVSEL/
(Driven by LSI53C895A)
AD[31:0]
C_BE[3:0]/
(Driven by Master)
FRAME/
(Driven by Master)
MAD
(Driven by LSI53C895A)
MAS1/
(Driven by LSI53C895A)
MAS0/
(Driven by LSI53C895A)
MCE/
(Driven by LSI53C895A)
MOE/
(Driven by LSI53C895A)
MWE/
(Driven by LSI53C895A)
17 18 19 20 21 22 23 24 25 26 27 28 29 30 31
Byte Enable
16 32 33
Low Order
Address
Data In
Data Out
(Driven by Master)
(Driven by Master)