Dma mode (dmode), Dma mode, Dmode) – Avago Technologies LSI53C895A User Manual
Page 175: If the rea, Mode (dmode), Scratch register a (scratcha), Scratch register a, Scratcha), Register: 0x38
SCSI Registers
4-67
Registers: 0x34–0x37
Scratch Register A (SCRATCHA)
Read/Write
SCRATCHA
Scratch Register A
[31:0]
This is a general purpose, user-definable scratch pad
register. Apart from CPU access, only Register
Read/Write and Memory Moves into the SCRATCH
register alter its contents. The power-up value of this
register is indeterminate.
A special mode of this register is enabled by setting the
PCI Configuration Into Enable bit in the
register. If this bit is set, the SCRATCH A
register returns bits [31:10] of the Memory Mapped
Operating register PCI base address (
) in bits [31:10] of the
when read. Bits [9:0] of SCRATCH
A will always return zero in this mode. Writes to the
SCRATCH A register are unaffected. Clearing the PCI
Configuration Into Enable bit causes the SCRATCH A
register to return to normal operation.
Register: 0x38
DMA Mode (DMODE)
Read/Write
BL[1:0]
Burst Length
[7:6]
These bits control the maximum number of Dwords
transferred per bus ownership, regardless of whether the
transfers are back-to-back, burst, or a combination of
both. The LSI53C895A asserts the Bus Request (REQ/)
output when the DMA FIFO can accommodate a transfer
of at least one burst threshold of data. Bus Request
(REQ/) is also asserted during start-of-transfer and
31
0
SCRATCHA
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
x
7
6
5
4
3
2
1
0
BL[1:0]
SIOM
DIOM
ERL
ERMP
BOF
MAN
0
0
0
0
0
0
0
0