Avago Technologies LSI53C895A - Manual (Page 221)

Phase Mismatch Jump Registers 4-113
the SCSI bus during data phases, i.e. it will not count
bytes sent in command, status, message in or message
out phases. It will count bytes as long as the phase
mismatch enable (ENPMJ) bit in the
Chip Control 0
(CCNTL0) register is set. Unlike the SCSI Byte Count
(SBC) this count will not be cleared on each BMOV
instruction but will continue to count across multiple
BMOV instructions. This register can be loaded with any
arbitrary start value.
Registers: 0xE0–0xFF
Reserved