8 mad bus programming, Mad bus programming, Section 3.8, “mad bus programming – Avago Technologies LSI53C895A User Manual
Page 107
MAD Bus Programming
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3.8 MAD Bus Programming
The MAD[7:0] pins, in addition to serving as the address/data bus for the
local memory interface, also are used to program power-up options for
the chip. A particular option is programmed allowing the internal
pull-down current sink to pull the pin LOW at reset or by connecting a
4.7 k
Ω
resistor between the appropriate MAD[x] pin and V
SS
. The
pull-down resistors require that HC or HCT external components are
used for the memory interface. The MAD[7:0] pins are sensed by internal
circuitry three PCI clock cycles after RST/ is deasserted.
•
MAD[7] – Serial EEPROM programmable option. When allowed to
be pulled LOW by the internal pull-down current sink, the automatic
data download is enabled. When pulled HIGH by an external resistor,
the automatic data download is disabled. Please see
in
and
and
registers in
for additional
information.
•
MAD[6] – This signal is Reserved and may be left floating.
•
MAD[5] – Enables duplicate SCSI SREQ/ and SACK/ signals. When
pulled LOW by the internal pull-down current sink, the duplicate SCSI
SREQ/ and SACK/ signals are disabled. When pulled HIGH by an
external resistor, the duplicate SCSI SREQ/ and SACK/ signals are
enabled. If these duplicate signals are enabled, they must also be
terminated.
•
MAD[4] – Enables the alternative SSVID/SSID loading mechanism
for
and
. When allowed to be
pulled LOW by the internal pull-down current sink, the alternative
SSVID/SSID loading mechanism for the
and
is enabled. When pulled HIGH by an external
resistor, the alternative loading mechanism for the
and
Vendor ID is disabled.
For additional information, see the two topics:
“Alternative SSVID/SSID Loading Mechanism,”
and
in