Avago Technologies LSI53C895A User Manual
Page 202
4-94
Registers
STR
SCSI FIFO Test Read
6
Setting this bit places the SCSI core into a test mode in
which the SCSI FIFO is easily read. Reading the least
significant byte of the
register causes the FIFO to unload. The functions are
summarized in the table below.
HSC
Halt SCSI Clock
5
Asserting this bit causes the internal divided SCSI clock
to come to a stop in a glitchless manner. This bit is used
for test purposes or to lower I
DD
during a power-down
mode.
DSI
Disable Single Initiator Response
4
If this bit is set, the LSI53C895A ignores all bus-initiated
selection attempts that employ the single initiator option
from SCSI-1. In order to select the LSI53C895A while this
bit is set, the LSI53C895A’s SCSI ID and the initiator’s
SCSI ID must both be asserted. Assert this bit in
SCSI-2 systems so that a single bit error on the SCSI bus
is not interpreted as a single initiator response.
S16
16-Bit System
3
If this bit is set, all devices in the SCSI system
implementation are assumed to be 16-bit. This causes
the LSI53C895A to always check the parity bit for SCSI
IDs [15:8] during bus-initiated selection or reselection,
assuming parity checking has been enabled. If an 8-bit
SCSI device attempts to select the LSI53C895A while
this bit is set, the LSI53C895A will ignore the selection
attempt. This is because the parity bit for IDs [15:8] will
not be driven. See the description of the Enable Parity
Checking bit in the
register
for more information.
TTM
Timer Test Mode
2
Asserting this bit facilitates testing of the selection
time-out, general purpose, and handshake-to-handshake
Register
Name
Register
Operation
FIFO Bits
FIFO
Function
SODL
Read
[15:0]
Unload
SODL0
Read
[7:0]
Unload
SODL1
Read
[15:8]
None