Avago Technologies LSI53C895A - Manual (Page 279)

PCI and External Memory Interface Timing Diagrams 6-19
Figure 6.14 64-Bit Address Operating Register/SCRIPTS RAM Read
Table 6.21 64-Bit Address Operating Register/SCRIPTS RAM Read
Symbol Parameter Min Max Unit
t
1
Shared signal input setup time 7 – ns
t
2
Shared signal input hold time 0 – ns
t
3
CLK to shared signal output valid – 11 ns
CLK
(Driven by System)
FRAME/
(Driven by Master)
AD[31:0]
(Driven by Master-Addr;
LSI53C895A-Data)
C_BE[3:0]
(Driven by Master)
PAR
(Driven by Master-Addr;
LSI53C895A-Data)
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C895A)
STOP/
(Driven by LSI53C895A)
DEVSEL/
(Driven by LSI53C895A)
t
1
t
2
t
3
Out In
Byte Enable
Bus Dual
Addr
Addr
Lo
Addr
Hi
Data
Out
t
1
t
1
t
1
t
2
t
2
t
2
t
2
t
1
t
1
t
3
t
3
t
3
t
3
In
CMD