Avago Technologies LSI53C895A - Manual (Page 11)

Contents xi
6.3 Rise and Fall Time Test Condition 6-9
6.4 SCSI Input Filtering 6-9
6.5 Hysteresis of SCSI Receivers 6-10
6.6 Input Current as a Function of Input Voltage 6-10
6.7 Output Current as a Function of Output Voltage 6-11
6.8 External Clock 6-12
6.9 Reset Input 6-13
6.10 Interrupt Output 6-14
6.11 PCI Configuration Register Read 6-16
6.12 PCI Configuration Register Write 6-17
6.13 32-Bit Operating Register/SCRIPTS RAM Read 6-18
6.14 64-Bit Address Operating Register/SCRIPTS RAM Read 6-19
6.15 32-Bit Operating Register/SCRIPTS RAM Write 6-20
6.16 64-Bit Address Operating Register/SCRIPTS RAM Write 6-21
6.17 Nonburst Opcode Fetch, 32-Bit Address and Data 6-23
6.18 Burst Opcode Fetch, 32-Bit Address and Data 6-25
6.19 Back to Back Read, 32-Bit Address and Data 6-27
6.20 Back to Back Write, 32-Bit Address and Data 6-29
6.21 Burst Read, 32-Bit Address and Data 6-31
6.22 Burst Read, 64-Bit Address and Data 6-33
6.23 Burst Write, 32-Bit Address and Data 6-35
6.24 Burst Write, 64-Bit Address and 32-Bit Data 6-37
6.25 External Memory Read 6-40
6.26 External Memory Write 6-44
6.27 Normal/Fast Memory (
≥
128 Kbytes) Single Byte
Access Read Cycle 6-46
6.28 Normal/Fast Memory (
≥
128 Kbytes) Single Byte
Access Write Cycle 6-47
6.29 Normal/Fast Memory (
≥
128 Kbytes) Multiple Byte
Access Read Cycle 6-48
6.30 Normal/Fast Memory (
≥
128 Kbytes) Multiple Byte
Access Write Cycle 6-50
6.31 Slow Memory (
≤
128 Kbytes) Read Cycle 6-52
6.32 Slow Memory (
≤
128 Kbytes) Write Cycle 6-53
6.33
≤
64 Kbytes ROM Read Cycle 6-54
6.34
≤
64 Kbyte ROM Write Cycle 6-55
6.35 Initiator Asynchronous Send 6-56
6.36 Initiator Asynchronous Receive 6-57