13 scsi bus interface, 1 lvdlink technology, Scsi bus interface – Avago Technologies LSI53C895A User Manual
Page 60
2-34
Functional Description
register and bits [7:0] of the DMA FIFO register.
AND the result with 0x3FF for a byte count between zero and
944.
Step 2.
Read the
register and examine bits
[7:4], the binary representation of the number of valid bytes in
the SCSI FIFO, to determine if any bytes are left in the SCSI
FIFO.
Step 3.
If any wide transfers have been performed using the Chained
Move instruction, read the Wide SCSI Receive bit (
, bit 0) to determine whether a byte is left
in the
register.
2.2.13 SCSI Bus Interface
The LSI53C895A performs SE and LVD transfers, and supports
traditional HVD operation when the chip is connected to external HVD
transceivers.
To support LVD SCSI, all SCSI data and control signals have both
negative and positive signal lines. The negative signals perform the SCSI
data and control function. In the SE mode the positive signals become
virtual ground drivers. In the HVD mode, the positive signals provide
directional control to the external transceivers. TolerANT technology
provides signal filtering at the inputs of SREQ/ and SACK/ to increase
immunity to signal reflections.
2.2.13.1 LVDlink Technology
To support greater device connectivity and a longer SCSI cable, the
LSI53C895A features LVDlink technology, the LSI Logic implementation
of LVD SCSI. LVDlink transceivers provide the inherent reliability of
differential SCSI, and a long-term migration path of faster SCSI transfer
rates.
LVDlink technology is based on current drive. Its low output current
reduces the power needed to drive the SCSI bus, so that the I/O drivers
can be integrated directly onto the chip. This reduces the cost and
complexity compared to traditional HVD designs. LVDlink lowers the
amplitude of noise reflections and allows higher transmission
frequencies.