Avago Technologies LSI53C895A - Manual (Page 141)

SCSI Registers 4-33
(This SCSI synchronous core clock is determined in
SCNTL3 bits [6:4], ExtCC = 1 if SCNTL1 bit 7 is asserted
and the LSI53C895A is sending data. ExtCC = 0 if the
LSI53C895A is receiving data.)
SXFERP = 100
÷
25 = 4
Where:
Table 4.3 shows examples of synchronous transfer periods and rates for
SCSI-1.
SXFERP Synchronous transfer period.
SSCP SCSI synchronous core period.
SSCF SCSI synchronous core frequency.
ExtCC Extra clock cycle of data setup.
Table 4.3 Examples of Synchronous Transfer Periods and Rates
for SCSI-1
CLK (MHz)
SCSI CLK
÷
SCNTL3
Bits [6:4]
XFERP
(SXFER
Bits [7:5])
Synch.
Transfer
Period (ns)
Synch.
Transfer Rate
(Mbytes/s)
66.67 3 4 180 5.55
66.67 3 5 225 4.44
50 2 4 160 6.25
50 2 5 200 5
40 2 4 200 5
37.50 1.5 4 160 6.25
33.33 1.5 4 180 5.55
25 1 4 160 6.25
20 1 4 200 5
16.67 1 4 240 4.17