Avago Technologies LSI53C895A - Manual (Page 169)

SCSI Registers 4-61
LSI53C895A is informed of the error by the PERR/ pin
being asserted by the target. When this bit is cleared, the
LSI53C895A does not interrupt if a master parity error
occurs. This bit is cleared at power-up.
FBL[2:0] FIFO Byte Control [2:0]
These bits steer the contents of the Chip Test Six
(CTEST6) register to the appropriate byte lane of the
64-bit DMA FIFO. If the FBL3 bit is set, then FBL2
through FBL0 determine which of eight byte lanes can be
read or written. When cleared, the byte lane read or
written is determined by the current contents of the
DMA
Next Address (DNAD) and DMA Byte Counter (DBC)
registers. Each of the eight bytes that make up the 64-bit
DMA FIFO is accessed by writing these bits to the proper
value. For normal operation, FBL3 must equal zero.
FBL3 FBL2 FBL1 FBL0
DMA FIFO
Byte Lane
0 x x x Disabled
1 0 0 0 0
1 0 0 1 1
1 0 1 0 2
1 0 1 1 3
1 1 0 0 4
1 1 0 1 5
1 1 1 0 6
1 1 1 1 7