Avago Technologies LSI53C895A - Manual (Page 293)

PCI and External Memory Interface Timing Diagrams 6-33
Figure 6.22 Burst Read, 64-Bit Address and Data
t
1
CLK
(Driven by System)
GPIO0_FETCH/
(Driven by LSI53C895A)
GPIO1_MASTER/
(Driven by LSI53C895A)
REQ/
(Driven by LSI53C895A)
PAR
(Driven by LSI53C895A)
IRDY/
(Driven by LSI53C895A)
TRDY/
(Driven by Target)
STOP/
(Driven by Target)
DEVSEL/
(Driven by Target)
AD
(Driven by LSI53C895A)
C_BE/
(Driven by LSI53C895A)
t
3
CMD
GNT/
(Driven by Arbiter)
FRAME/
(Driven by LSI53C895A)
Addr
Out
t
2
BE
Data
Out
Data
Out
t
1
t
2