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Figure6.40 lsi53c895a 272-pin bga top view, Lsi53c895a 272-pin bga top view, Figure 6.40 – Avago Technologies LSI53C895A User Manual

Page 325

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Figure 6.40 LSI53C895A 272-Pin BGA Top View

A1

A2

A3

A4

A5

A6

A7

A8

A9

A10

A11

A12

A13

A14

A15

A16

A17

A18

A19

A20

VSS

N/C

SD2+

SD3+

SD4+

N/C

SD5-

SD6-

SD7-

RBIAS

VDD_

BIAS

SATN+

SBSY+

SACK+

SRST+

SMSG+

SSEL+

SSEL-

N/C

N/C

B1

B2

B3

B4

B5

B6

B7

B8

B9

B10

B11

B12

B13

B14

B15

B16

B17

B18

B19

B20

N/C

SD1+

SD1-

SD2-

SD3-

SD4-

SD5+

SD6+

SD7+

SDP0-

N/C

SATN-

SBSY-

SACK-

SRST-

SMSG-

N/C

N/C

SREQ2+

SREQ2-

C1

C2

C3

C4

C5

C6

C7

C8

C9

C10

C11

C12

C13

C14

C15

C16

C17

C18

C19

C20

SD0-

N/C

N/C

N/C

N/C

N/C

N/C

N/C

N/C

SDP0+

N/C

N/C

N/C

N/C

N/C

N/C

SCD-

N/C

SREQ+

SIO-

D1

D2

D3

D4

D5

D6

D7

D8

D9

D10

D11

D12

D13

D14

D15

D16

D17

D18

D19

D20

SD0+

SACK2-

SACK2+

VSS

N/C

VDD

N/C

VSS

N/C

N/C

VDD

N/C

VSS

N/C

VDD

SCD+

VSS

SREQ-

SD8+

SD8-

E1

E2

E3

E4

E17

E18

E19

E20

SDP1-

N/C

N/C

N/C

SIO+

N/C

SD9+

SD9-

F1

F2

F3

F4

F17

F18

F19

F20

SD15+

SD15-

SDP1+

VDD

VDD

N/C

SD10+

SD10-

G1

G2

G3

G4

G17

G18

G19

G20

SD14+

SD14-

N/C

N/C

N/C

N/C

SD11+

SD11-

H1

H2

H3

H4

H17

H18

H19

H20

SD13+

SD13-

N/C

VSS

VSS

N/C

VDDA

DIFFSENS

J1

J2

J3

J4

J9

J10

J11

J12

J17

J18

J19

J20

N/C

SD12+

SD12-

N/C

VSS

VSS

VSS

VSS

N/C

VSSA

TEST_

HSC/

SCLK

K1

K2

K3

K4

K9

K10

K11

K12

K17

K18

K19

K20

TCK

TEST_

RST/

N/C

VDD

VSS

VSS

VSS

VSS

N/C

N/C

MAC/_

TESTOUT

MAD0

L1

L2

L3

L4

L9

L10

L11

L12

L17

L18

L19

L20

TMS

TDO

TDI

N/C

VSS

VSS

VSS

VSS

VDD

N/C

MAD2

MAD1

M1

M2

M3

M4

M9

M10

M11

M12

M17

M18

M19

M20

MAS1/

MAS0/

VSS_

CORE

N/C

VSS

VSS

VSS

VSS

N/C

MAD5

MAD4

MAD3

N1

N2

N3

N4

N17

N18

N19

N20

VSS_

CORE2

MWE/

MOE/

VSS

VSS

VSS_

CORE

MAD7

MAD6

P1

P2

P3

P4

P17

P18

P19

P20

VDD_

CORE

VDD_

CORE

N/C

N/C

VDD_

CORE

GPIO3

GPIO4

VSS_

CORE

R1

R2

R3

R4

R17

R18

R19

R20

MCE/

RST/

N/C

VDD

VDD

GPIO_

MASTER/

VDD_

CORE

GPIO2

T1

T2

T3

T4

T17

T18

T19

T20

CLK

GNT/

N/C

N/C

N/C

N/C

GPIO0_
FETCH/

N/C

U1

U2

U3

U4

U5

U6

U7

U8

U9

U10

U11

U12

U13

V14

U15

U16

U17

U18

U19

U20

REQ/

AD31

N/C

VSS

N/C

VDD

N/C

VSS

C_BE2/

VDD

SERR/

N/C

VSS

N/C

VDD

N/C

VSS

AD1

N/C

IRQ/

V1

V2

V3

V4

V5

V6

V7

V8

V9

V10

V11

V12

V13

V14

V15

V16

V17

V18

V19

V20

AD30

AD29

AD27

N/C

AD25

IDSEL

AD21

AD18

FRAME/

N/C

PERR/

AD15

AD12

N/C

N/C

N/C

AD4

AD2

GPIO7

AD0

W1

W2

W3

W4

W5

W6

W7

W8

W9

W10

W11

W12

W13

W14

W15

W16

W17

W18

W19

W20

AD28

GPIO8

N/C

N/C

AD24

AD23

AD20

AD17

IRDY/

TRDY/

STOP/

C_BE1/

AD13

AD10

AD8

N/C

AD6

N/C

GPIO5

GPIO6

Y1

Y2

Y3

Y4

Y5

Y6

Y7

Y8

Y9

Y10

Y11

Y12

Y13

Y14

Y15

Y16

Y17

Y18

Y19

Y20

TRST

ALT_IRQ/

AD26

N/C

C_BE3/

AD22

AD19

AD16

N/C

DEVSEL/

N/C

PAR

AD14

AD11

AD9

C_BE0/

AD7

AD5

AD3

N/C