Avago Technologies LSI53C895A - Manual (Page 297)

PCI and External Memory Interface Timing Diagrams 6-37
Figure 6.24 Burst Write, 64-Bit Address and 32-Bit Data
t
1
CLK
(Driven by System)
GPIO0_FETCH/
(Driven by LSI53C895A)
GPIO1_MASTER/
(Driven by LSI53C895A)
REQ/
(Driven by LSI53C895A)
PAR;
(Driven by LSI53C895A)
IRDY/
(Driven by LSI53C895A)
TRDY/
(Driven by Target)
STOP/
(Driven by Target)
DEVSEL/
(Driven by Target)
AD[31:0]
(Driven by LSI53C895A)
C_BE[3:0]/
(Driven by LSI53C895A)
t
3
GNT/
(Driven by Arbiter)
FRAME/
(Driven by LSI53C895A)
Addr
Out Lo
t
2
Addr
Out Hi
Bus Dual
Addr CMD
Data
Out
Data
Out
BE BE
t
3
t
1
t
2