Avago Technologies LSI53C895A - Manual (Page 313)

PCI and External Memory Interface Timing Diagrams 6-53
Figure 6.32 Slow Memory (
≤ =
128 Kbytes) Write Cycle
Table 6.37 Slow Memory (
≤ =
128 Kbytes) Write Cycle
Symbol Parameter Min Max Unit
t
11
Address setup to MAS/ HIGH 25 – ns
t
12
Address hold from MAS/ HIGH 15 – ns
t
13
MAS/ pulse width 25 – ns
t
20
Data setup to MWE/ LOW 30 – ns
t
21
Data hold from MWE/ HIGH 20 – ns
t
22
MWE/ pulse width 100 – ns
t
23
Address setup to MWE/ LOW 60 – ns
t
24
MCE/ LOW to MWE/ HIGH 120 – ns
t
25
MCE/ LOW to MWE/ LOW 25 – ns
t
26
MWE/ HIGH to MCE/ HIGH 25 – ns
CLK
MAD
(Driven by LSI53C895A)
MAS1/
(Driven by LSI53C895A)
MAS0/
(Driven by LSI53C895A)
MCE/
(Driven by LSI53C895A)
MOE/
(Driven by LSI53C895A)
MWE/
(Driven by LSI53C895A)
Higher
Address
Lower
Address
t
12
Middle
Address
Valid Write Data
t
11
t
13
t
21 t
22
t
20
t
23
t
24
t
25 t
26