5 designing an ultra2 scsi system, 1 using the scsi clock quadrupler, Designing an ultra2 scsi system – Avago Technologies LSI53C895A User Manual
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Functional Description
2.2.5 Designing an Ultra2 SCSI System
Since Ultra2 SCSI is based on existing SCSI standards, it can use
existing driver programs as long as the software is able to negotiate for
Ultra2 SCSI synchronous transfer rates. Additional software
modifications are needed to take advantage of the new features in the
LSI53C895A.
In the area of hardware, LVD SCSI is required to achieve Ultra2 SCSI
transfer rates and to support the longer cable and additional devices on
the bus. All devices on the bus must have LVD SCSI capabilities to
guarantee Ultra2 SCSI transfer rates. For additional information on Ultra2
SCSI, refer to the SPI-2 working document which is available from the
SCSI BBS referenced at the beginning of this manual.
Chapter 6, “Electrical Specifications,”
contains Ultra2 SCSI timing
information. In addition to the guidelines in the draft standard, make the
following software and hardware adjustments to accommodate Ultra2
SCSI transfers:
•
Set the Ultra Enable bit to enable Ultra2 SCSI transfers.
•
Set the TolerANT Enable bit, bit 7 in the
register, whenever the Ultra Enable bit is set.
•
Do not extend the SREQ/SACK filtering period with
bit 1. When the Ultra Enable bit is set, the filtering period
is fixed at 8 ns for Ultra2 SCSI or 15 ns for Ultra SCSI, regardless of
the value of the SREQ/SACK Filtering bit.
•
Use the SCSI clock quadrupler.
A 40 MHz input must be supplied if using the SCSI clock quadrupler
for an Ultra2 design.
2.2.5.1 Using the SCSI Clock Quadrupler
The LSI53C895A can quadruple the frequency of a 40 MHz SCSI clock,
allowing the system to perform Ultra2 SCSI transfers. This option is user
selectable with bit settings in the
, and
registers. At
power-on or reset, the quadrupler is disabled and powered down. Follow
these steps to use the clock quadrupler: