Avago Technologies LSI53C895A - Manual (Page 23)

LSI53C895A Benefits Summary 1-7
•
Performs sustained memory-to-memory DMA transfers to
approximately 100 Mbytes/s.
•
Minimizes SCSI I/O start latency.
•
Performs complex bus sequences without interrupts, including
restoring data pointers.
•
Reduces ISR overhead through a unique interrupt status reporting
method.
•
Uses Load/Store SCRIPTS instructions which increase performance
of data transfers to and from the chip registers without using PCI
cycles.
•
Has SCRIPTS support for 64-bit addressing.
•
Supports multithreaded I/O algorithms in SCSI SCRIPTS with fast
I/O context switching.
•
Supports additional arithmetic capability with the Expanded Register
Move instruction.
1.5.2 PCI Performance
To improve PCI performance, the LSI53C895A:
•
Complies with PCI 2.2 specification.
•
Supports 32-bit 33 MHz PCI interface with 64-bit addressing.
•
Supports dual address cycles which can be generated for all
SCRIPTS for > 4 Gbyte addressability.
•
Bursts 2, 4, 8, 16, 32, 64, or 128 Dword transfers across the PCI bus.
•
Supports 32-bit word data bursts with variable burst lengths.
•
Prefetches up to 8 Dwords of SCRIPTS instructions.
•
Bursts SCRIPTS opcode fetches across the PCI bus.
•
Performs zero wait-state bus master data bursts faster than
110 Mbytes/s (@ 33 MHz).
•
Supports PCI Cache Line Size register.
•
Supports PCI Write and Invalidate, Read Line, and Read Multiple
commands.
•
Complies with PCI Bus Power Management Specification
Revision 1.1.