Avago Technologies LSI53C895A - Manual (Page 310)

6-50 Electrical Specifications
Figure 6.30 Normal/Fast Memory (
≥ =
128 Kbytes) Multiple Byte Access Write Cycle
CLK
(Driven by System)
PAR
IRDY/
(Driven by Master)
TRDY/
(Driven by LSI53C895A)
STOP/
(Driven by LSI53C895A)
DEVSEL/
(Driven by LSI53C895A)
AD[31:0]
C_BE[3:0]/
(Driven by Master)
FRAME/
(Driven by Master)
MAD
(Driven by LSI53C895A)
MAS1/
(Driven by LSI53C895A)
MAS0/
(Driven by LSI53C895A)
MCE/
(Driven by LSI53C895A)
MOE/
(Driven by LSI53C895A)
MWE/
(Driven by LSI53C895A)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
In
Addr
CMD
In
High Order
Address
Order
Address
Middle
Order
Address
Low
Data Out
Data
In
Byte
Enable
In
(Driven by Master)
(Driven by Master)