Avago Technologies LSI53C895A - Manual (Page 14)

xiv Contents
6.15 External Clock 6-12
6.16 Reset Input 6-13
6.17 Interrupt Output 6-14
6.18 PCI Configuration Register Read 6-16
6.19 PCI Configuration Register Write 6-17
6.20 32-Bit Operating Register/SCRIPTS RAM Read 6-18
6.21 64-Bit Address Operating Register/SCRIPTS RAM Read 6-19
6.22 32-Bit Operating Register/SCRIPTS RAM Write 6-20
6.23 64-Bit Address Operating Register/SCRIPTS RAM Write 6-21
6.24 Nonburst Opcode Fetch, 32-Bit Address and Data 6-22
6.25 Burst Opcode Fetch, 32-Bit Address and Data 6-24
6.26 Back to Back Read, 32-Bit Address and Data 6-26
6.27 Back to Back Write, 32-Bit Address and Data 6-28
6.28 Burst Read, 32-Bit Address and Data 6-30
6.29 Burst Read, 64-Bit Address and Data 6-32
6.30 Burst Write, 32-Bit Address and Data 6-34
6.31 Burst Write, 64-Bit Address and 32-Bit Data 6-36
6.32 External Memory Read 6-39
6.33 External Memory Write 6-43
6.34 Normal/Fast Memory (
≥
128 Kbytes) Single Byte Access
Read Cycle 6-46
6.35 Normal/Fast Memory (
≥
128 Kbytes) Single Byte Access
Write Cycle 6-47
6.36 Slow Memory (
≤
128 Kbytes) Read Cycle 6-52
6.37 Slow Memory (
≤
128 Kbytes) Write Cycle 6-53
6.38
≤ =
64 Kbytes ROM Read Cycle 6-54
6.39
≤
64 Kbyte ROM Write Cycle 6-55
6.40 Initiator Asynchronous Send 6-56
6.41 Initiator Asynchronous Receive 6-57
6.42 Target Asynchronous Send 6-58
6.43 Target Asynchronous Receive 6-59
6.44 SCSI-1 Transfers (SE 5.0 Mbytes) 6-59
6.45 SCSI-1 Transfers (Differential 4.17 Mbytes) 6-60
6.46 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or
20.0 Mbytes (16-Bit Transfers) 40 MHz Clock
6-60
6.47 SCSI-2 Fast Transfers 10.0 Mbytes (8-Bit Transfers) or
20.0 Mbytes (16-Bit Transfers) 50 MHz Clock
6-61