Avago Technologies LSI53C895A - Manual (Page 52)

2-26 Functional Description
2.2.10 SCSI Loopback Mode
The LSI53C895A loopback mode allows testing of both initiator and
target functions and, in effect, lets the chip communicate with itself.
When the Loopback Enable bit is set in the
SCSI Test Two (STEST2)
register, bit 4, the LSI53C895A allows control of all SCSI signals whether
the chip is operating in the initiator or target mode. For more information
on this mode of operation refer to the LSI Logic SCSI SCRIPTS
Processors Programming Guide.
2.2.11 Parity Options
The LSI53C895A implements a flexible parity scheme that allows control
of the parity sense, allows parity checking to be turned on or off, and has
the ability to deliberately send a byte with bad parity over the SCSI bus
to test parity error recovery procedures.
Table 2.3 defines the bits that
are involved in parity control and observation. Table 2.4 describes the
parity control function of the Enable Parity Checking and Assert SCSI
Even Parity bits in the
SCSI Control One (SCNTL1) register, bit 2.
Table 2.5 describes the options available when a parity error occurs.
Figure 2.2 shows where parity checking is done in the LSI53C895A.