Avago Technologies LSI53C895A User Manual
Page 232
5-10
SCSI SCRIPTS Instruction Set
register during a receive operation. This byte is
combined with the first byte from the subsequent transfer
so that a wide transfer can be completed.
5.
If the SATN/ signal is asserted by the Initiator or a parity
error occurred during the transfer, the transfer can
optionally be halted and an interrupt generated. The
Disable Halt on Parity Error or ATN bit in the
register controls whether the LSI53C895A
halts on these conditions immediately, or waits until
completion of the current Move.
Initiator Mode
In Target mode, the OpCode bit defines the following
operations:
These instructions perform the following steps:
1.
The LSI53C895A verifies that it is connected to the SCSI
bus as an Initiator before executing this instruction.
2.
The LSI53C895A waits for an unserviced phase to occur.
An unserviced phase is any phase (with SREQ/ asserted)
for which the LSI53C895A has not yet transferred data by
responding with a SACK/.
3.
The LSI53C895A compares the SCSI phase bits in the
register with the latched SCSI
phase lines stored in the
register. These phase lines are latched when SREQ/ is
asserted.
4.
If the SCSI phase bits match the value stored in the SCSI
transfers the number of bytes specified in the
register starting at the address pointed to
by the
register. If the OpCode
bit is cleared and a data transfer ends on an odd byte
boundary, the LSI53C895A stores the last byte in the
register during a receive operation,
OPC
Instruction Defined
0
CHMOV
1
MOVE