Avago Technologies LSI53C895A - Manual (Page 353)

Index IX-7
M
MAC/_TESTOUT 3-14
MAD
bus 2-56
bus programming 3-19
pins 2-56
MAD[0] 3-20
MAD[3:1] 3-20
MAD[4] 3-19
MAD[5] 3-19
MAD[6] 3-19
MAD[7:0] 3-15
MAD[7:0] pins 3-19
MAD[7] 3-19
mailbox one (MBOX1) 4-53
mailbox zero (MBOX0) 4-53
manual start mode (MAN) 4-69
MAS0/ 3-14
MAS1/ 3-15
masking 2-46
master
control for set or reset pulses (MASR) 4-62
data parity error (MDPE) 4-41 , 4-70
enable (ME) 4-84
parity error enable (MPEE) 4-60
max SCSI synchronous offset (MO[4:0]) 4-34
MAX_LAT (ML) 4-15
maximum stress ratings 6-2
MCE/ 3-14
memory
access control 3-14
access control (MACNTL) 4-83
address strobe 0 3-14
address strobe 1 3-15
address/data bus 3-15
chip enable 3-14
I/O address/DSA offset 5-37
move 2-9
move instructions 2-23 , 5-32
no flush option 2-24
move read selector (MMRS) 4-104
move write selector (MMWS) 4-105
output enable 3-14
read 2-10 , 2-11
read caching 2-11
read command 2-5
read line 2-10 , 2-11
read line command 2-7
read multiple 2-10 , 2-11
read multiple command 2-6
space 2-2 , 2-3
to memory 2-18
to memory moves 2-18
write 2-10 , 2-11
write and invalidate 2-10
write and invalidate command 2-8
write caching 2-11
write command 2-5
write enable 3-14
MIN_GNT (MG) 4-14
MOE/ 3-14
move to/from SFBR cycles 5-24
multiple cache line transfers 2-8
MWE/ 3-14
N
new capabilities (NC) 4-6
new features in the LSI53C895A 1-3
Next_Item_Ptr (NIP) 4-15
no connections 3-18
no download mode 2-58
no flush 5-33
store instruction only 5-36
not supported 4-9 , 4-10
O
opcode 5-8 , 5-13 , 5-22 , 5-26
fetch burst capability 2-24
operating conditions 6-2
operator 5-22
P
PAR 3-6
parallel ROM interface 2-55
parallel ROM support 2-56
parity 2-28 , 3-6
error 3-8
error (PAR) 4-79
options 2-26
PCI
addressing 2-2
and external memory interface timing diagrams 6-14
bus commands and encoding types 2-4
bus commands and functions supported 2-4
cache line size register 2-8
cache mode 2-9
commands 2-4
configuration into enable (PCICIE) 4-55
configuration register read 6-16
configuration registers 4-1
configuration space 2-2
functional description 2-2
I/O space 2-3
interface signals 3-4
master transaction 2-10
master transfer 2-10
memory space 2-3
performance 1-7
target disconnect 2-9
target retry 2-9
PERR/ 3-8
phase mismatch
handling in SCRIPTS 2-19
jump address 1 (PMJAD1) 4-108
jump address 2 (PMJAD2) 4-109
jump registers 4-108
physical dword address and data 3-5
PME
_enable (PEN) 4-17
_support (PMES) 4-16
clock (PMEC) 4-16
status (PST) 4-17
pointer SCRIPTS (PSCPT) 4-83
polling 2-43
power
and ground signals 3-17
management 2-60