Avago Technologies LSI53C895A - Manual (Page 160)

4-52 Registers
Register: 0x15
Interrupt Status One (ISTAT1)
Read/Write
R Reserved [7:3]
FLSH Flushing 2
Reading this bit monitors if the chip is currently flushing
data. If set, the chip is flushing data from the DMA FIFO.
If cleared, no flushing is occurring. This bit is read only
and writes will have no effect on the value of this bit.
SRUN SCRIPTS Running 1
This bit indicates whether or not the SCRIPTS engine is
currently fetching and executing SCRIPTS instructions. If
this bit is set, the SCRIPTS engine is active.
If it is cleared, the SCRIPTS engine is not active.
This bit is read only and writes will have no effect on the
value of this bit.
SI SYNC_IRQD 0
Setting this bit disables the IRQ/ pin. Clearing this bit
enables normal operation of the IRQ/ pin. The function of
this bit is nearly identical to bit 1 of the
DMA Control
(DCNTL) ( 0x3B ) register except that if the IRQ/ is already
asserted and this bit is set, IRQ/ will remain asserted until
the interrupt is serviced. At this point the IRQ/ line will be
blocked for future interrupts until this bit is cleared. In
addition, this bit may be read and written while SCRIPTS
are executing.
7 3 2 1 0
R FLSH SRUN SI
x x x x x 0 0 0